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general description the max1436b octal, 12-bit analog-to-digital converter (adc) features fully differential inputs, a pipelined architecture, and digital error correction incorporating a fully differential signal path. this adc is optimized for low-power and high-dynamic performance in medical imaging instrumentation and digital communications applications. the max1436b operates from a 1.8v sin- gle supply and consumes only 743mw (93mw per channel) while delivering a 69.9db (typ) signal-to-noise ratio (snr) at a 5.3mhz input frequency. in addition to low operating power, the max1436b features a low- power standby mode for idle periods. an internal 1.24v precision bandgap reference sets the full-scale range of the adc. a flexible reference struc- ture allows the use of an external reference for applica- tions requiring increased accuracy or a different input voltage range. the reference architecture is optimized for low noise. a single-ended clock controls the data-conversion process. an internal duty-cycle equalizer compensates for wide variations in clock duty cycle. an on-chip pll generates the high-speed serial low-voltage differential signal (lvds) clock. the max1436b has self-aligned serial lvds outputs for data, clock, and frame-alignment signals. the output data is presented in two? complement or binary format. the max1436b offers a maximum sample rate of 40msps. see the pin-compatible versions table below for higher-speed versions. this device is available in a small, 14mm x 14mm x 1mm, 100-pin tqfp package with exposed pad and is specified for the extended industrial (-40? to +85?) temperature range. applications ultrasound and medical imaging instrumentation multichannel communications features excellent dynamic performance 69.9db snr at 5.3mhz 96dbc sfdr at 5.3mhz 95db channel isolation ultra-low power 93mw per channel (normal operation) fast 200s wake-up time from standby serial lvds outputs pin-selectable lvds/slvs (scalable low-voltage signal) mode lvds outputs support up to 30 inches fr-4 backplane connections test mode for digital signal integrity fully differential analog inputs wide differential input voltage range (1.4v p-p ) on-chip 1.24v precision bandgap reference clock duty-cycle equalizer compact, 100-pin tqfp package with exposed pad evaluation kit available (order max1436bevkit) max1436b octal, 12-bit, 40msps, 1.8v adc with serial lvds outputs ________________________________________________________________ maxim integrated products 1 ordering information 19-0523; rev 1; 2/11 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pin configuration appears at the end of data sheet. evaluation kit available pa r t t em p ra n g epin - pa c k a g e m ax 1436be c q+ d - 40c to + 85 c 100 tqfp - e p * ( 14m m x 14m m x 1m m ) pin-compatible versions part sampling rate (msps) resolution (bits) power- save mode MAX1434 50 10 power-down max1436 40 12 power-down max1436b 40 12 standby max1437 50 12 power-down max1438 65 12 power-down + denotes a lead(pb)-free/rohs-compliant package. d = dry pack. * ep = exposed pad.
max1436b octal, 12-bit, 40msps, 1.8v adc with serial lvds outputs 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (voltages referenced to gnd) avdd.....................................................................-0.3v to +2.0v cvdd.....................................................................-0.3v to +3.6v ovdd ....................................................................-0.3v to +2.0v in_p, in_n ..............................................-0.3v to (v av dd + 0.3v) clk ........................................................-0.3v to (v cv dd + 0.3v) out_p, out_n, frame_, clkout_ ......-0.3v to (v ov dd + 0.3v) dt, slvs/ lvds , lvdstest, pll_, t /b, stby, refio, refadj, cmout...................-0.3v to (v av dd + 0.3v) continuous power dissipation (t a = +70?) tqfp (derate 47.6mw/? above +70?) ................3809.5mw operating temperature range ...........................-40? to +85? maximum junction temperature .....................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) .......................................+260? electrical characteristics (v av dd = 1.8v, v ov dd = 1.8v, v cv dd = 3.3v, v gnd = 0v, external v refio = 1.24v, c refio = 0.1?, c refp = 10?, c refn = 10?, f clk = 40mhz (50% duty cycle), v dt = 0v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (notes 2, 3) parameter symbol conditions min typ max units dc accuracy (note 4) resolution n 12 bits integral nonlinearity inl ?.4 ? lsb differential nonlinearity dnl no missing codes over temperature ?.25 ? lsb offset error ?.5 %fs gain error ?.4 %fs analog inputs (in_p, in_n) input differential range v id differential input 1.4 v p-p common-mode voltage range v cmo 0.76 v common-mode voltage range tolerance (note 5) ?0 mv differential input impedance r in switched capacitor load 2 k differential input capacitance c in 12.5 pf conversion rate maximum conversion rate f smax 40 mhz minimum conversion rate f smin 4.0 mhz data latency 6.5 cycles package thermal characteristics (note 1) note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . tqfp junction-to-ambient thermal resistance ( ja ) ...........21?/w junction-to-case thermal resistance ( jc ) ..................2?/w
max1436b octal, 12-bit, 40msps, 1.8v adc with serial lvds outputs _______________________________________________________________________________________ 3 electrical characteristics (continued) (v av dd = 1.8v, v ov dd = 1.8v, v cv dd = 3.3v, v gnd = 0v, external v refio = 1.24v, c refio = 0.1?, c refp = 10?, c refn = 10?, f clk = 40mhz (50% duty cycle), v dt = 0v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (notes 2, 3) parameter symbol conditions min typ max units dynamic characteristics (differential inputs, 4096-point fft) (note 4) f in = 5.3mhz at -0.5dbfs 69.9 signal-to-noise ratio snr f in = 19.3mhz at -0.5dbfs 66.5 69.6 db f in = 5.3mhz at -0.5dbfs 69.9 signal-to-noise and distortion (first 4 harmonics) sinad f in = 19.3mhz at -0.5dbfs 66.5 69.6 db f in = 5.3mhz at -0.5dbfs 11.3 effective number of bits enob f in = 19.3mhz at -0.5dbfs 11.3 db f in = 5.3mhz at -0.5dbfs 96 spurious-free dynamic range sfdr f in = 19.3mhz at -0.5dbfs 79 90 dbc f in = 5.3mhz at -0.5dbfs -96 total harmonic distortion thd f in = 19.3mhz at -0.5dbfs -92 -79 dbc intermodulation distortion imd f 1 = 5.3mhz at -6.5dbfs f 2 = 6.3mhz at -6.5dbfs 89.8 dbc third-order intermodulation im3 f 1 = 5.3mhz at -6.5dbfs f 2 = 6.3mhz at -6.5dbfs 96.6 dbc aperture jitter t aj figure 11 < 0.4 ps rms aperture delay t ad figure 11 1 ns small-signal bandwidth ssbw input at -20dbfs 100 mhz full-power bandwidth lsbw input at -0.5dbfs 100 mhz output noise in_p = in_n 0.44 lsb rms over-range recovery time t or r s = 25 , c s = 50pf 1 clock cycle internal reference refadj internal reference-mode enable voltage (note 6) 0.1 v refadj low-leakage current 1.5 ma refio output voltage v refio 1.18 1.24 1.30 v reference temperature coefficient tc refio 120 ppm/? external reference refadj external reference- mode enable voltage (note 6) v avdd - 0.1 v refadj high-leakage current 200 ? refio input voltage 1.24 v refio input voltage tolerance ? % refio input current i refio < 1 a
max1436b octal, 12-bit, 40msps, 1.8v adc with serial lvds outputs 4 _______________________________________________________________________________________ electrical characteristics (continued) (v av dd = 1.8v, v ov dd = 1.8v, v cv dd = 3.3v, v gnd = 0v, external v refio = 1.24v, c refio = 0.1?, c refp = 10?, c refn = 10?, f clk = 40mhz (50% duty cycle), v dt = 0v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (notes 2, 3) parameter symbol conditions min typ max units common-mode output (cmout) cmout output voltage v cmout 0.76 v clock input (clk) input high voltage v clkh 0.8 x v avdd v input low voltage v clkl 0.2 x v avdd v clock duty cycle 50 % clock duty-cycle tolerance ?0 % input at gnd 5 input leakage current di in input at avdd 80 ? input capacitance dc in 5pf digital inputs (pll_, lvdstest, dt, slvs, stby, t /b) input logic-high voltage v ih 0.8 x v avdd v input logic-low voltage v il 0.2 x v avdd v input at gnd 5 input leakage current di in input at avdd 80 ? input capacitance dc in 5pf lvds outputs (out_p, out_n), slvs/ lvds = 0 differential output voltage v ohdiff r term = 100 250 450 mv output common-mode voltage v ocm r term = 100 1.125 1.375 v rise time (20% to 80%) t rl r term = 100 , c load = 5pf 350 ps fall time (80% to 20%) t fl r term = 100 , c load = 5pf 350 ps slvs outputs (out_p, out_n, clkoutp, clkoutn, framep, framen), slvs/ lvds = 1, dt = 1 differential output voltage v ohdiff r term = 100 205 mv output common-mode voltage v ocm r term = 100 220 mv rise time (20% to 80%) t rs r term = 100 , c load = 5pf 320 ps fall time (80% to 20%) t fs r term = 100 , c load = 5pf 320 ps standby mode (stby) stby fall to output enable t enable 200 ? stby rise to output disable t disable 60 ns
max1436b octal, 12-bit, 40msps, 1.8v adc with serial lvds outputs _______________________________________________________________________________________ 5 electrical characteristics (continued) (v av dd = 1.8v, v ov dd = 1.8v, v cv dd = 3.3v, v gnd = 0v, external v refio = 1.24v, c refio = 0.1?, c refp = 10?, c refn = 10?, f clk = 40mhz (50% duty cycle), v dt = 0v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (notes 2, 3) parameter symbol conditions min typ max units power requirements avdd supply voltage range v avdd 1.7 1.8 1.9 v ovdd supply voltage range v ovdd 1.7 1.8 1.9 v cvdd supply voltage range v cvdd 1.7 1.8 3.6 v stby = 0 337 380 stby = 0, d t = 1 337 ma avdd supply current i avdd f in = 19.3mhz at -0.5dbfs stby = 1, standb y, no cl ock i np ut 37 ma stby = 0 76 100 stby = 0, d t = 199 ma ovdd supply current i ovdd f in = 19.3mhz at -0.5dbfs stby = 1, standb y, no cl ock i np ut 16 ? cvdd supply current i cvdd cvdd is used only to bias esd-protection diodes on clk input, figure 2 0ma power dissipation p diss f in = 19.3mhz at -0.5dbfs 743 864 mw timing characteristics (note 8) data valid to clkout rise/fall t od figure 5 (notes 7, 8) ( t s am p le /24) - 0.15 ( t s am p le /24) + 0.15 ns clkout output-width high t ch figure 5 t s am p le /12 ns clkout output-width low t cl figure 5 t s am p le /12 ns frame rise to clkout rise t cf figure 4 (note 8) ( t s am p le /24) - 0.15 ( t s am p le /24) + 0.15 ns sample clk rise to frame rise t sf figure 4 (note 8) ( t s am p le /2) + 1.1 ( t s am p le /2) + 2.6 ns crosstalk (note 4) -95 db gain matching c gm f in = 5.3mhz (note 4) ?.1 db phase matching c pm f in = 5.3mhz (note 4) ?.25 d eg r ees note 2: specifications at t a +25? are guaranteed by production testing. specifications at t a < +25? are guaranteed by design and characterization and not subject to production testing. note 3: all capacitances are between the indicated pin and gnd, unless otherwise noted. note 4: see definition in the parameter definitions section at the end of this data sheet. note 5: see the common-mode output (cmout) section. note 6: connect refadj to gnd directly to enable internal reference mode. connect refadj to avdd directly to disable the inter- nal bandgap reference and enable external reference mode. note 7: data valid to clkout rise/fall timing is measured from 50% of data output level to 50% of clock output level. note 8: guaranteed by design and characterization. not subject to production testing.
max1436b octal, 12-bit, 40msps, 1.8v adc with serial lvds outputs 6 _______________________________________________________________________________________ max1436b toc04 frequency ( mhz ) amplitude (dbfs) 0 -10 -20 -30 -40 -50 -70 -60 -80 -100 -90 -110 51015 020 two-tone intermodulation distortion (16,384-point data record) f in(in1) = 5.298993mhz f in(in2) = 6.298573mhz a in1 = -6.5dbfs a in2 = -6.5dbfs imd = 89.8dbc im3 = 96.6dbc 1 -1 -10 1 100 1000 -6 -7 -8 -9 -5 -4 -3 -2 max1436b toc05 analog input frequency ( mhz ) gain (db) 10 bandwidth vs. analog input frequency 0 full-power bandwidth -0.5dbfs small-signal bandwidth -20.5dbfs signal-to-noise ratio vs. analog input frequency analog input frequency ( mhz ) snr (db) 100 80 20 40 60 63 64 65 67 69 66 68 70 71 max1436b toc06 72 62 0 120 signal-to-noise plus distortion vs. analog input frequency analog input frequency (mhz) sinad (db) 100 80 20 40 60 63 64 65 67 69 66 68 70 71 max1436b toc07 72 62 0120 total harmonic distortion vs. analog input frequency analog input frequency (mhz) thd (dbc) 100 80 20 40 60 -95 -90 -85 -75 -70 -80 -65 -60 max1436b toc08 -55 -100 0120 spurious-free dynamic range vs. analog input frequency analog input frequency (mhz) sfdr (dbc) 100 80 20 40 60 60 65 70 80 85 75 90 95 max1436b toc09 100 55 0 120 typical operating characteristics (v av dd = 1.8v, v ov dd = 1.8v, v cv dd = 3.3v, v gnd = 0v, internal reference, differential input at -0.5dbfs, f in = 5.3mhz, f clk = 40mhz (50% duty cycle), v dt = 0v, c load = 10pf, t a = +25?, unless otherwise noted.) fft plot (16,384-point data record) max1436b toc01 frequency (mhz) amplitude (dbfs) 0 -10 -20 -30 -40 -50 -70 -60 -80 -100 -90 -110 51015 020 f clk = 39.8871375mhz f in = 5.304814mhz a in = -0.5dbfs snr = 69.917db sinad = 69.907db thd = -96.178dbc sfdr = 95.807dbc hd2 hd3 fft plot (16,384-point data record) max1436b toc02 frequency (mhz) amplitude (dbfs) 0 -10 -20 -30 -40 -50 -70 -60 -80 -100 -90 -110 f clk = 39.8871374mhz f in = 19.2984215mhz a in = -0.5dbfs snr = 69.641db sinad = 69.618db thd = -92.410dbc sfdr = 90.384dbc 51015 020 hd2 hd3 crosstalk (16,384-point data record) max1436b toc03 frequency (mhz) amplitude (dbfs) 0 -10 -20 -30 -40 -50 -70 -60 -80 -100 -110 -90 51015 020 measured on channel 1, with interfering signal on channel 2 f in(in1) = 5.304814mhz f in(in2) = 19.2984215mhz crosstalk = 97.2db f in(in2)
max1436b octal, 12-bit, 40msps, 1.8v adc with serial lvds outputs _______________________________________________________________________________________ 7 typical operating characteristics (continued) (v av dd = 1.8v, v ov dd = 1.8v, v cv dd = 3.3v, v gnd = 0v, internal reference, differential input at -0.5dbfs, f in = 5.3mhz, f clk = 40mhz (50% duty cycle), v dt = 0v, c load = 10pf, t a = +25?, unless otherwise noted.) signal-to-noise ratio vs. analog input power analog input power (dbfs) snr (db) -5 -10 -25 -20 -15 37 42 52 57 47 62 67 72 32 -30 0 max1436b toc10 f in = 5.304814mhz signal-to-noise plus distortion vs. analog input power analog input power (dbfs) sinad (db) -5 -10 -25 -20 -15 37 42 52 57 47 62 max1436b toc11 67 72 32 -30 0 f in = 5.304814mhz total harmonic distortion vs. analog input power analog input power (dbfs) thd (dbc) -5 -10 -25 -20 -15 -80 -85 -75 -65 -60 -70 -55 -50 -45 -95 -90 -30 0 max1436b toc12 f in = 5.304814mhz spurious-free dynamic range vs. analog input power analog input power (dbfs) sfdr (dbc) -5 -10 -25 -20 -15 60 55 65 75 80 70 85 90 95 45 50 -30 0 max1436b toc13 f in = 5.304814mhz signal-to-noise ratio vs. sampling rate clock frequency (mhz) snr (db) 35 30 15 20 25 65 64 66 68 69 67 70 71 72 62 63 10 40 max1436b toc14 f in = 5.304814mhz signal-to-noise plus distortion vs. sampling rate clock frequency (mhz) sinad (db) 35 30 15 20 25 65 64 66 68 69 67 70 71 72 62 63 10 40 max1436b toc15 f in = 5.304814mhz total harmonic distortion vs. sampling rate clock frequency (mhz) thd (dbc) 35 15 20 25 30 -95 -90 -100 -85 -80 -75 -105 10 40 max1436b toc16 f in = 5.304814mhz spurious-free dynamic range vs. sampling rate clock frequency (mhz) sfdr (dbc) 35 15 20 25 30 85 90 80 95 100 105 75 10 40 max1436b toc17 f in = 5.304814mhz signal-to-noise ratio vs. duty cycle duty cycle (%) snr (db) 60 65 55 40 45 35 50 69 66 72 67 68 70 71 73 65 30 70 max1436b toc18 f in = 5.304814mhz
max1436b octal, 12-bit, 40msps, 1.8v adc with serial lvds outputs 8 _______________________________________________________________________________________ signal-to-noise ratio vs. temperature temperature ( c) snr (db) -15 10 60 35 68 70 69 67 66 72 71 73 65 -40 85 max1436b toc22 f clk = 40mhz f in = 19.8mhz 4096-point data record signal-to-noise plus distortion vs. temperature temperature ( c) sinad (db) -15 10 60 35 68 70 69 67 66 72 71 73 65 -40 85 max1436b toc23 f clk = 40mhz f in = 19.8mhz 4096-point data record total harmonic distortion vs. temperature temperature ( c) thd (dbc) -15 10 60 35 -95 -93 -94 -96 -99 -97 -98 -91 -92 -90 -100 -40 85 max1436b toc24 f clk = 40mhz f in = 19.8mhz 4096-point data record spurious-free dynamic range vs. temperature temperature ( c) sfdr (dbc) -15 10 60 35 90 92 91 89 86 88 87 94 93 95 85 -40 85 max1436b toc25 f clk = 40mhz f in = 19.8mhz 4096-point data record 280 300 290 320 310 330 340 350 360 01015 5 2025303540 supply current vs. sampling rate (avdd) max1436b toc26 clock frequency (mhz) i avdd (ma) 55 60 70 65 75 80 85 01015 5 2025303540 analog supply current vs. sampling rate (0vdd) max1436b toc27 clock frequency (mhz) i ovdd (ma) signal-to-noise plus distortion vs. duty cycle duty cycle (%) sinad (db) 60 65 55 40 45 35 50 69 66 72 67 68 70 71 73 65 30 70 max1436b toc19 f in = 5.304814mhz total harmonic distortion vs. duty cycle duty cycle (%) thd (dbc) 60 65 55 40 45 35 50 -90 -100 -80 -95 -85 -75 -105 30 70 max1436b toc20 f in = 5.304814mhz spurious-free dynamic range vs. duty cycle duty cycle (%) sfdr (dbc) 60 65 55 40 45 35 50 85 75 95 80 90 100 70 30 70 max1436b toc21 f in = 5.304814mhz typical operating characteristics (continued) (v av dd = 1.8v, v ov dd = 1.8v, v cv dd = 3.3v, v gnd = 0v, internal reference, differential input at -0.5dbfs, f in = 5.3mhz, f clk = 40mhz (50% duty cycle), v dt = 0v, c load = 10pf, t a = +25?, unless otherwise noted.)
max1436b octal, 12-bit, 40msps, 1.8v adc with serial lvds outputs _______________________________________________________________________________________ 9 typical operating characteristics (continued) (v av dd = 1.8v, v ov dd = 1.8v, v cv dd = 3.3v, v gnd = 0v, internal reference, differential input at -0.5dbfs, f in = 5.3mhz, f clk = 40mhz (50% duty cycle), v dt = 0v, c load = 10pf, t a = +25?, unless otherwise noted.) offset error vs. temperature temperature ( c) offset error (%fs) -15 10 60 35 0 -0.01 0.01 0.02 -0.03 -0.02 0.03 0.04 -0.04 -40 85 max1436b toc28 gain error vs. temperature temperature ( c) gain error (%fs) -15 10 60 35 0.2 0.6 -0.2 -0.6 0 0.4 -0.4 -0.8 0.8 1.0 -1.0 -40 85 max1436b toc29 integral nonlinearity vs. digital output code max1436b toc30 digital output code inl (lsb) 1024 3072 2048 512 2560 3584 1536 -0.3 0 -0.4 0.4 -0.2 0.2 -0.1 0.3 0.1 0.5 -0.5 0 4096 differential nonlinearity vs. digital output code max1436b toc31 digital output code dnl (lsb) 1024 3072 2048 512 2560 3584 1536 -0.2 0 -0.1 0.1 0.2 0.3 -0.3 0 4096 internal reference voltage vs. supply voltage supply voltage (v) v refio (v) 2.0 1.9 1.8 1.2480 1.2490 1.2500 1.2510 1.2470 1.7 2.1 max1436b toc32 v avdd = v ovdd internal reference voltage vs. temperature temperature ( c) v refio (v) 60 35 10 -15 1.23 1.24 1.25 1.26 1.22 -40 85 max1436b toc33 v avdd = v ovdd
max1436b octal, 12-bit, 40msps, 1.8v adc with serial lvds outputs 10 ______________________________________________________________________________________ internal reference voltage vs. reference load current i refio ( a) v refio (v) -250 -150 50 250 150 -50 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 1.00 -350 350 max1436b toc34 cmout voltage vs. supply voltage supply voltage (v) v cmout (v) 2.0 1.9 1.8 0.764 0.762 0.766 0.768 0.770 0.760 1.7 2.1 max1436b toc35 v avdd = v ovdd cmout voltage vs. temperature temperature ( c) v cmout (v) 60 35 10 -15 0.764 0.766 0.768 0.770 0.760 0.762 -40 85 max1436b toc36 v avdd = v ovdd cmout voltage vs. load current i cmout ( a) v cmout (v) 1500 1000 500 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 2000 max1436b toc37 69.0 69.3 69.9 69.6 70.2 70.5 75 125 100 150 175 200 225 250 snr/sinad vs. stby delay time max1436b toc38 stby delay time ( s) snr/sinad (db) f in = 5.2966309 mhz a in = -0. 5dbfs data based on 32,768 data points snr sinad 92.0 94.0 98.0 96.0 100.0 102.0 75 125 100 150 175 200 225 250 -thd/sfdr vs. stby delay time max1436b toc39 stby delay time ( s) -thd/sfdr (dbc) f in = 5.2966309 mhz a in = -0. 5dbfs data based on 32,768 data points sfdr -thd typical operating characteristics (continued) (v av dd = 1.8v, v ov dd = 1.8v, v cv dd = 3.3v, v gnd = 0v, internal reference, differential input at -0.5dbfs, f in = 5.3mhz, f clk = 40mhz (50% duty cycle), v dt = 0v, c load = 10pf, t a = +25?, unless otherwise noted.)
max1436b octal, 12-bit, 40msps, 1.8v adc with serial lvds outputs ______________________________________________________________________________________ 11 pin name function 1, 4, 7, 10, 16, 19, 22, 25, 26, 27, 30, 36, 89, 92, 96, 99, 100 gnd ground. connect all gnd pins to the same potential. 2 in1p channel 1 positive analog input 3 in1n channel 1 negative analog input 5 in2p channel 2 positive analog input 6 in2n channel 2 negative analog input 8 in3p channel 3 positive analog input 9 in3n channel 3 negative analog input 11, 12, 13, 15, 37?2, 86, 87, 88 avdd analog power input. connect avdd to a 1.7v to 1.9v power supply. bypass avdd to gnd with a 0.1? capacitor as close as possible to the device. bypass the avdd power plane to the gnd plane with a bulk 2.2? capacitor. connect all avdd pins to the same potential. 14, 31, 50, 51, 70, 75, 76 n.c. no connection. not internally connected. 17 in4p channel 4 positive analog input 18 in4n channel 4 negative analog input 20 in5p channel 5 positive analog input 21 in5n channel 5 negative analog input 23 in6p channel 6 positive analog input 24 in6n channel 6 negative analog input 28 in7p channel 7 positive analog input 29 in7n channel 7 negative analog input 32 dt double-termination select. drive dt high to select the internal 100 termination between the differential output pairs. drive dt low to select no output termination. 33 slvs/ lvds differential output-signal format-select input. drive slvs/ lvds high to select slvs outputs. drive slvs/ lvds low to select lvds outputs. 34 cvdd clock power input. connect cvdd to a 1.7v to 3.6v power supply. bypass cvdd to gnd with a 0.1? capacitor in parallel with a 2.2? capacitor. install the bypass capacitors as close as possible to the device. 35 clk single-ended cmos clock input 43, 46, 49, 54, 57, 60, 63, 64, 67, 71, 74, 77 ovdd o utp ut- d r i ver p ow er inp ut. c onnect o v d d to a 1.7v to 1.9v p ow er sup p l y. byp ass o v d d to g n d w i th a 0.1f cap aci tor as cl ose as p ossi b l e to the d evi ce. byp ass the o v d d p ow er p l ane to the g n d p l ane w i th a b ul k 2.2f cap aci tor . c onnect al l o v d d p i ns to the sam e p otenti al . 44 out7n channel 7 negative lvds/slvs output 45 out7p channel 7 positive lvds/slvs output 47 out6n channel 6 negative lvds/slvs output 48 out6p channel 6 positive lvds/slvs output 52 out5n channel 5 negative lvds/slvs output 53 out5p channel 5 positive lvds/slvs output 55 out4n channel 4 negative lvds/slvs output 56 out4p channel 4 positive lvds/slvs output pin description
max1436b octal, 12-bit, 40msps, 1.8v adc with serial lvds outputs 12 ______________________________________________________________________________________ pin name function 58 framen negative frame-alignment lvds/slvs output. a rising edge on the differential frame output aligns to a valid d0 in the output data stream. 59 framep positive frame-alignment lvds/slvs output. a rising edge on the differential frame output aligns to a valid d0 in the output data stream. 61 clkoutn negative lvds/slvs serial clock output 62 clkoutp positive lvds/slvs serial clock output 65 out3n channel 3 negative lvds/slvs output 66 out3p channel 3 positive lvds/slvs output 68 out2n channel 2 negative lvds/slvs output 69 out2p channel 2 positive lvds/slvs output 72 out1n channel 1 negative lvds/slvs output 73 out1p channel 1 positive lvds/slvs output 78 out0n channel 0 negative lvds/slvs output 79 out0p channel 0 positive lvds/slvs output 80 lvdstest lvds test pattern enable. drive lvdstest high to enable the output test pattern (0000 1011 1101 msb lsb). as with the analog conversion results, the test pattern data is output lsb first. drive lvdstest low for normal operation. 81 stby standby input. an active-high level on stby puts the max1436b into standby mode, leaving the reference circuitry active. drive stby low for normal operation. 82 pll3 pll control input 3. see table 1 for details. 83 pll2 pll control input 2. see table 1 for details. 84 pll1 pll control input 1. see table 1 for details. 85 t /b output format-select input. drive t /b high to select binary output format. drive t /b low to select two?-complement output format. 90 refn n eg ati ve refer ence byp ass o utp ut. c onnect a 1? ( 10? typ ) cap aci tor b etw een re fp and re fn , and connect a 1? ( 10? typ ) cap aci tor b etw een re fn and gn d . pla c e t h e c a p a c it o r s a s c lo s e as p o s s ib le t o t h e de v i c e on t h e sa m e si d e of t h e pc b . 91 refp positive reference bypass output. connect a 1? (10? typ) capacitor between refp and refn, and connect a 1? (10? typ) capacitor between refp and gnd. place the capacitors as close as possible to the device on the same side of the pc b . 93 refio reference input/output. for internal reference operation (refadj = gnd), the reference output voltage is 1.24v. for external reference operation (refadj = avdd), apply a stable reference voltage at refio. bypass to gnd with 0.1?. 94 refadj internal/external reference-mode-select and reference adjust input. for internal reference mode, connect refadj directly to gnd. for external reference mode, connect refadj directly to avdd. for reference-adjust mode, see the full-scale range adjustments using the internal reference section. 95 cmout common-mode reference voltage output. cmout outputs the input common-mode voltage for dc-coupled applications. bypass cmout to gnd with 0.1? capacitor. 97 in0p channel 0 positive analog input 98 in0n channel 0 negative analog input ep exposed pad. ep is internally connected to gnd. connect ep to gnd. pin description (continued)
max1436b octal, 12-bit, 40msps, 1.8v adc with serial lvds outputs ______________________________________________________________________________________ 13 detailed description the max1436b adc features fully differential inputs, a pipelined architecture, and digital error correction for high-speed signal conversion. the adc pipeline archi- tecture moves the samples taken at the inputs through the pipeline stages every half clock cycle. the convert- ed digital results are serialized and sent through the lvds/slvs output drivers. the total clock-cycle latency from input to output is 6.5 clock cycles. the max1436b offers eight separate fully differential channels with synchronized inputs and outputs. configure the outputs for binary or two? complement with the t /b digital input. global power-down minimizes power consumption. input circuit figure 1 displays a simplified diagram of the input t/h circuits. in track mode, switches s1, s2a, s2b, s4a, s4b, s5a, and s5b are closed. the fully differential circuits sample the input signals onto the two capacitors (c2a and c2b) through switches s4a and s4b. s2a and s2b set the common mode for the operational transconduc- tance amplifier (ota), and open simultaneously with s1, sampling the input waveform. switches s4a, s4b, s5a, and s5b are then opened before switches s3a and s3b connect capacitors c1a and c1b to the output of the amplifier and switch s4c is closed. the resulting differ- ential voltages are held on capacitors c2a and c2b. the amplifiers charge capacitors c1a and c1b to the same values originally held on c2a and c2b. these values are then presented to the first-stage quantizers and isolate lvds/slvs output drivers pll 6x clock circuitry reference system in0p in0n in1p in1n in7p in7n clk refadj refio refp refn out0p out0n out1p out1n out7p out7n ovdd avdd gnd cvdd pll3 pll1 pll2 lvdstest dt output control max1436b t/h 12-bit pipeline adc 12:1 serializer t/h 12-bit pipeline adc 12:1 serializer framep framen clkoutp clkoutn t/h 12-bit pipeline adc 12:1 serializer power control stby slvs/lvds t/b *icmv = input common-mode voltage (internally generated). cmout icmv* functional diagram
max1436b octal, 12-bit, 40msps, 1.8v adc with serial lvds outputs 14 ______________________________________________________________________________________ the pipelines from the fast-changing inputs. analog inputs, in_p to in_n, are driven differentially. for differ- ential inputs, balance the input impedance of in_p and in_n for optimum performance. reference configurations (refio, refadj, refp, and refn) the max1436b provides an internal 1.24v bandgap reference or can be driven with an external reference voltage. the full-scale analog differential input range is ?sr. fsr (full-scale range) is given by the following equation: where v refio is the voltage at refio, generated inter- nally or externally. for a v refio = 1.24v, the full-scale input range is ?00mv (1.4v p-p ). internal reference mode connect refadj to gnd to use the internal bandgap reference directly. the internal bandgap reference gen- erates v refio to be 1.24v with a 120ppm/? tempera- ture coefficient in internal reference mode. connect an external 0.1? bypass capacitor from refio to gnd for stability. refio sources up to 200? and sinks up to 200? for external circuits, and refio has a 75mv/ma load regulation. putting the max1436b into standby mode turns off all circuitry except the refer- ence circuit, allowing the converter to power-up faster when the adc exits standby with a high-to-low transi- tional signal on stby. the internal circuits of the max1436b require 200? to power up and settle when the converter exits standby mode. to compensate for gain errors or to decrease or increase the adc? fsr, add an external resistor between refadj and gnd or refadj and refio. this adjusts the internal reference value of the max1436b by up to ?% of its nominal value. see the full-scale range adjustments using the internal reference section. fsr v v refio = (. ) . 0 700 124 max1436b in_p in_n ota avdd gnd c2a s4b s4c s1 c2b s4a c1a s2a s5a s3a s3b s5b c1b s2b internal bias* out internally generated common-mode level* switches shown in track mode internally generated common-mode level* internal common-mode bias* internal common-mode bias* *not externally accessible internal bias * out figure 1. internal input circuit
max1436b octal, 12-bit, 40msps, 1.8v adc with serial lvds outputs ______________________________________________________________________________________ 15 connect 1? (10? typ) capacitors to gnd from refp and refn and a 1? (10? typ) capacitor between refp and refn as close to the device as possible on the same side of the pc board. external reference mode the external reference mode allows for more control over the max1436b reference voltage and allows multi- ple converters to use a common reference. connect refadj to avdd to disable the internal reference. apply a stable 1.18v to 1.30v source at refio. bypass refio to gnd with a 0.1? capacitor. the refio input impedance is > 1m . clock input (clk) the max1436b accepts a cmos-compatible clock sig- nal with a wide 20% to 80% input clock duty cycle. drive clk with an external single-ended clock signal. figure 2 shows the simplified clock input diagram. low clock jitter is required for the specified snr perfor- mance of the max1436b. analog input sampling occurs on the rising edge of clk, requiring this edge to provide the lowest possible jitter. jitter limits the maxi- mum snr performance of any adc according to the following relationship: where f in represents the analog input frequency and t j is the total system clock jitter. pll inputs (pll1, pll2, pll3) the max1436b features a pll that generates an output clock signal with 6 times the frequency of the input clock. the output clock signal is used to clock data out of the max1436b (see the system timing requirements section). set the pll1, pll2, and pll3 bits according to the input clock range provided in table 1. system timing requirements figure 3 shows the relationship between the analog inputs, input clock, frame-alignment output, serial-clock output, and serial-data output. the differential analog input (in_p and in_n) is sampled on the rising edge of the clk signal and the resulting data appears at the digital outputs 6.5 clock cycles later. figure 4 provides a detailed, two-conversion timing diagram of the rela- tionship between the inputs and the outputs. clock output (clkoutp, clkoutn) the max1436b provides a differential clock output that consists of clkoutp and clkoutn. as shown in figure 4, the serial output data is clocked out of the max1436b on both edges of the clock output. the frequency of the output clock is 6 times the frequency of clk. frame-alignment output (framep, framen) the max1436b provides a differential frame-alignment signal that consists of framep and framen. as shown in figure 4, the rising edge of the frame-align- ment signal corresponds to the first bit (d0) of the 12- bit serial data stream. the frequency of the frame- alignment signal is identical to the frequency of the input clock. serial output data (out_p, out_n) the max1436b provides its conversion results through individual differential outputs consisting of out_p and out_n. the results are valid 6.5 input clock cycles after the sample is taken. as shown in figure 3, the out- put data is clocked out on both edges of the output clock, lsb (d0) first. figure 5 provides the detailed ser- ial-output timing diagram. snr ft in j = ? ? ? ? ? ? 20 1 2 log max1436b duty-cycle equalizer avdd cvdd clk gnd figure 2. clock input circuitry input clock range (mhz) pll1 pll2 pll3 min max 0 0 0 unused 0 0 1 32.5 40.0 0 1 0 22.5 32.5 0 1 1 16.3 22.5 1 0 0 11.3 16.3 1 0 1 8.1 11.3 1 1 0 5.6 8.1 1 1 1 4.0 5.6 table 1. pll1, pll2, and pll3 configuration table
max1436b octal, 12-bit, 40msps, 1.8v adc with serial lvds outputs 16 ______________________________________________________________________________________ output data for sample n - 6 output data for sample n *duty cycle varies depending on input clock frequency. clk n n + 2 n + 1 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8 n + 9 6.5 clock-cycle data latency t sample (v in_p - v in_n ) (v framep - v framen )* (v clkoutp - v clkoutn ) (v out_p - v out_n ) figure 3. global timing diagram n n + 2 n + 1 *duty cycle depends on input clock frequency. t cf (v in_p - v in_n ) clk (v framep - v framen )* (v clkoutp - v clkoutn ) (v out_p - v out_n ) d5 n-7 d6 n-7 d7 n-7 d8 n-7 d9 n-7 d10 n-7 d11 n-7 d0 n-6 d1 n-6 d2 n-6 d3 n-6 d4 n-6 d5 n-6 d6 n-6 d7 n-6 d8 n-6 d9 n-6 d10 n-6 d11 n-6 d0 n-5 d1 n-5 d2 n-5 d3 n-5 d4 n-5 d5 n-5 d6 n-5 t sample t sf figure 4. detailed two-conversion timing diagram (v clkoutp - v clkoutn ) (v out_p - v out_n ) t ch t cl t od t od d0 d1 d2 d3 figure 5. serialized-output detailed timing diagram
max1436b octal, 12-bit, 40msps, 1.8v adc with serial lvds outputs ______________________________________________________________________________________ 17 output data format ( t /b) transfer functions the max1436b output data format is either offset bina- ry or two? complement, depending on the logic-input t /b. with t /b low, the output data format is two? com- plement. with t /b high, the output data format is offset binary. the following equations, table 2, and figures 6 and 7 define the relationship between the digital output and the analog input. for two? complement ( t /b = 0): and for offset binary ( t /b = 1): where code 10 is the decimal equivalent of the digital output code as shown in table 2. keep the capacitive load on the max1436b digital out- puts as low as possible. v v fsr code in p in n __ ?= ? 2 2048 4096 10 v v fsr code in p in n __ ?= 2 4096 10 two?-complement digital output code ( t /b = 0) offset binary digital output code ( t /b = 1) binary d11 d0 hexadecimal equivalent of d11 d0 decimal equivalent of d11 d0 binary d11 d0 hexadecimal equivalent of d11 d0 decimal equivalent of d11 d0 v in _ p - v in _ n ( mv ) ( v refio = 1.24v ) 0111 1111 1111 0x7ff +2047 1111 1111 1111 0xfff +4095 +699.66 0111 1111 1110 0x7fe +2046 1111 1111 1110 0xffe +4094 +699.32 0000 0000 0001 0x001 +1 1000 0000 0001 0x801 +2049 +0.34 0000 0000 0000 0x000 0 1000 0000 0000 0x800 +2048 0 1111 1111 1111 0xfff -1 0111 1111 1111 0x7ff +2047 -0.34 1000 0000 0001 0x801 -2047 0000 0000 0001 0x001 +1 -699.66 1000 0000 0000 0x800 -2048 0000 0000 0000 0x000 0 -700.00 table 2. output code table (v refio = 1.24v) differential input voltage (lsb) -2045 +2047 +2045 -1 0 +1 -2047 0x800 0x801 0x802 0x803 0x7ff 0x7fe 0x7fd 0xfff 0x000 0x001 fsr fsr 1 lsb = 2 x fsr 4096 fsr = 700mv x v refio 1.24v two's-complement output code (lsb) figure 6. two?-complement transfer function ( t /b = 0) differential input voltage (lsb) -2045 +2047 +2045 -1 0 +1 -2047 0x000 0x800 0x002 0x003 0xfff 0xffe 0xffd 0x7ff 0x800 0x801 fsr fsr 1 lsb = 2 x fsr 4096 fsr = 700mv x v refio 1.24v offset binary output code (lsb) figure 7. binary transfer function ( t /b = 1)
max1436b octal, 12-bit, 40msps, 1.8v adc with serial lvds outputs 18 ______________________________________________________________________________________ lvds and slvs signals (slvs/ lvds ) drive slvs/ lvds low for lvds or drive slvs/ lvds high for slvs levels at the max1436b outputs (out_p, out_n, clkoutp, clkoutn, framep, and framen). for slvs levels, enable double-termination by driving dt high. see the electrical characteristics table for lvds and slvs output voltage levels. lvds test pattern (lvdstest) drive lvdstest high to enable the output test pattern on all lvds or slvs output channels. the output test pattern is 0000 1011 1101. drive lvdstest low for normal operation (test pattern disabled). common-mode output (cmout) cmout provides a common-mode reference for dc- coupled analog inputs. if the input is dc-coupled, match the output common-mode voltage of the circuit driving the max1436b to the output voltage at v cmout to within ?0mv. it is recommended that the output common-mode voltage of the driving circuit be derived from cmout. double-termination (dt) the max1436b offers an optional, internal 100 termina- tion between the differential output pairs (out_p and out_n, clkoutp and clkoutn, framep and fra- men). in addition to the termination at the end of the line, a second termination directly at the outputs helps eliminate unwanted reflections down the line. this feature is useful in applications where trace lengths are long (> 5in) or with mismatched impedance. drive dt high to select double- termination, or drive dt low to disconnect the internal ter- mination resistor (single-termination). selecting double-termination increases the ovdd supply current (see figure 8). standby mode the max1436b offers a standby mode to efficiently use power by transitioning to a low-power state when con- versions are not required. stby controls the standby mode of all channels and the internal reference circuitry. the reference does not power down in standby mode. drive stby high to enable standby. in standby mode, the output impedance of all of the lvds/slvs outputs is approximately 342 , if dt is low. the output impedance of the differential lvds/slvs outputs is 100 when dt is high. see the electrical characteristics table for typi- cal supply currents during standby. the following list shows the state of the analog inputs and digital outputs in standby mode: in_p, in_n analog inputs are disconnected from the internal input amplifier reference circuit remains active out_p, out_n, clkoutp, clkoutn, framep, and framen have approximately 342 between the output pairs when dt is low. when dt is high, the dif- ferential output pairs have 100 between each pair. when operating in internal reference mode, the max1436b requires 200? to power up and settle when the converter exits standby mode. to exit standby mode, stby, the applied control signal must transition from high to low. when using an external reference, the wake- up time is dependent on the external reference drivers. applications information full-scale range adjustments using the internal reference the max1436b supports a full-scale adjustment range of 10% (?%). to decrease the full-scale range, add a 25k to 250k external resistor or potentiometer (r adj ) between refadj and gnd. to increase the full- scale range, add a 25k to 250k resistor between refadj and refio. figure 9 shows the two possible configurations. the following equations provide the relationship between r adj and the change in the analog full-scale range: for r adj connected between refadj and refio, and: fsr v k r adj =+ ? ? ? ? ? ? 07 1 125 . . max1436b 100 100 out_p/ clkoutp/ framep out_n/ clkoutn/ framen dt switches are closed when dt is high. switches are open when dt is low. z 0 = 50 z 0 = 50 figure 8. double-termination
max1436b octal, 12-bit, 40msps, 1.8v adc with serial lvds outputs ______________________________________________________________________________________ 19 for r adj connected between refadj and gnd. using transformer coupling an rf transformer (figure 10) provides an excellent solution to convert a single-ended input source signal to a fully differential signal. the max1436b input com- mon-mode voltage is internally biased to 0.76v (typ) with f clk = 40mhz. although a 1:1 transformer is shown, a step-up transformer can be selected to reduce the drive requirements. a reduced signal swing from the input driver, such as an op amp, can also improve the overall distortion. grounding, bypassing, and board layout the max1436b requires high-speed board layout design techniques. refer to the MAX1434/max1436/ max1436b/max1437/max1438 ev kit data sheet for a board layout reference. locate all bypass capacitors as close to the device as possible, preferably on the same side as the adc, using surface-mount devices for mini- mum inductance. bypass avdd to gnd with a 0.1? ceramic capacitor in parallel with a 0.1? ceramic capacitor. bypass ovdd to gnd with a 0.1? ceramic capacitor in parallel with a 2.2? ceramic capacitor. bypass cvdd to gnd with a 0.1? ceramic capacitor in parallel with a 2.2? ceramic capacitor. multilayer boards with ample ground and power planes produce the highest level of signal integrity. connect max1436b ground pins and the exposed pad to the same ground plane. the max1436b relies on the exposed-backside-pad connection for a low-induc- tance ground connection. isolate the ground plane from any noisy digital system ground planes. route high-speed digital signal traces away from the sensitive analog traces. keep all signal lines short and free of 90 turns. ensure that the differential analog input network layout is symmetric and that all parasitics are balanced equally. refer to the MAX1434/max1436/max1436b/max1437/ max1438 ev kit data sheet for an example of symmetric input layout. parameter definitions integral nonlinearity (inl) integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. for the max1436b, this straight line is between the end points of the transfer function, once offset and gain errors have been nullified. inl deviations are measured at every step and the worst-case deviation is reported in the electrical characteristics table. differential nonlinearity (dnl) differential nonlinearity is the difference between an actual step width and the ideal value of 1 lsb. a dnl error specification of less than 1 lsb guarantees no missing codes and a monotonic transfer function. for the max1436b, dnl deviations are measured at every step and the worst-case deviation is reported in the electrical characteristics table. fsr v k r adj = ? ? ? ? ? ? ? 07 1 125 . . reference buffer refio refadj avdd avdd/2 control line to disable reference buffer adc full-scale = reft - refb g 1v 0.1 f reference- scaling amplifier reft refb 25k 250k 25k 250k max1436b figure 9. circuit suggestions to adjust the adc? full-scale range max1436b v in 0.1 f 0.1 f n.c. 1 2 3 6 5 4 t1 minicircuits adt1-1wt 10 10 39pf 39pf in_p in_n figure 10. transformer-coupled input drive
max1436b octal, 12-bit, 40msps, 1.8v adc with serial lvds outputs 20 ______________________________________________________________________________________ offset error offset error is a figure of merit that indicates how well the actual transfer function matches the ideal transfer function at a single point. for the max1436b, the ideal midscale digital output transition occurs when there is -1/2 lsbs across the analog inputs (figures 6 and 7). bipolar offset error is the amount of deviation between the measured midscale transition point and the ideal midscale transition point. gain error gain error is a figure of merit that indicates how well the slope of the actual transfer function matches the slope of the ideal transfer function. for the max1436b the gain error is the difference of the measured full-scale and zero-scale transition points minus the difference of the ideal full-scale and zero-scale transition points. for the bipolar devices (max1436b), the full-scale tran- sition point is from 0x7fe to 0x7ff for two?-comple- ment output format (0xffe to 0xfff for offset binary) and the zero-scale transition point is from 0x800 to 0x801 for two? complement (0x000 to 0x001 for offset binary). crosstalk crosstalk indicates how well each analog input is isolated from the others. for the max1436b, a 5.3mhz, -0.5dbfs analog signal is applied to one channel while a 19.3mhz, -0.5dbfs analog signal is applied to another channel. an fft is taken on the channel with the 5.3mhz analog sig- nal. from this fft, the crosstalk is measured as the dif- ference in the 5.3mhz and 19.3mhz amplitudes. aperture delay aperture delay (t ad ) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken. see figure 11. aperture jitter aperture jitter (t aj ) is the sample-to-sample variation in the aperture delay. see figure 11. signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digital samples, the theoretical maximum snr is the ratio of the full-scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum analog-to-digital noise is caused by quantiza- tion error only and results directly from the adc? reso- lution (n bits): snr db[max] = 6.02 db x n x 1.76 db in reality, there are other noise sources besides quantiza- tion noise: thermal noise, reference noise, clock jitter, etc. for the max1436b, snr is computed by taking the ratio of the rms signal to the rms noise. rms noise includes all spectral components to the nyquist fre- quency excluding the fundamental, the first six harmon- ics (hd2?d7), and the dc offset. signal-to-noise plus distortion (sinad) sinad is computed by taking the ratio of the rms signal to the rms noise plus distortion. rms noise plus distor- tion includes all spectral components to the nyquist fre- quency, excluding the fundamental and the dc offset. effective number of bits (enob) enob specifies the dynamic performance of an adc at a specific input frequency and sampling rate. an ideal adc? error consists of quantization noise only. enob for a full-scale sinusoidal input waveform is computed from: total harmonic distortion (thd) thd is the ratio of the rms sum of the first six harmon- ics of the input signal to the fundamental itself. this is expressed as: spurious-free dynamic range (sfdr) sfdr is the ratio expressed in decibels of the rms amplitude of the fundamental (maximum signal compo- nent) to the rms value of the next-largest spurious thd vvvvvv v = +++++ ? ? ? ? ? ? ? ? 20 2 2 3 2 4 2 5 2 6 2 7 2 1 log enob sinad = ? ? ? ? ? ? ? 176 602 . . clk analog input sampled data t/h t ad hold track hold t aj figure 11. aperture jitter/delay specifications
max1436b octal, 12-bit, 40msps, 1.8v adc with serial lvds outputs ______________________________________________________________________________________ 21 component, excluding dc offset. sfdr is specified in decibels relative to the carrier (dbc). intermodulation distortion (imd) imd is the total power of the im2 to im5 intermodulation products to the nyquist frequency relative to the total input power of the two input tones f 1 and f 2 . the indi- vidual input tone levels are at -6.5dbfs. the intermodu- lation products are as follows: 2nd-order intermodulation products (im2): f 1 + f 2 , f 2 - f 1 3rd-order intermodulation products (im3): 2 x f 1 - f 2 , 2 x f 2 - f 1 , 2 x f 1 + f 2 , 2 x f 2 + f 1 4th-order intermodulation products (im4): 3 x f 1 - f 2 , 3 x f 2 - f 1 , 3 x f 1 + f 2 , 3 x f 2 + f 1 5th-order intermodulation products (im5): 3 x f 1 - 2 x f 2 , 3 x f 2 - 2 x f 1 , 3 x f 1 + 2 x f 2 , 3 x f 2 + 2 x f 1 third-order intermodulation (im3) im3 is the total power of the 3rd-order intermodulation product to the nyquist frequency relative to the total input power of the two input tones f 1 and f 2 . the indi- vidual input tone levels are at -6.5dbfs. the 3rd-order intermodulation products are 2 x f 1 - f 2 , 2 x f 2 - f 1 , 2 x f 1 + f 2 , 2 x f 2 + f 1 . small-signal bandwidth a small -20.5dbfs analog input signal is applied to an adc so that the signal? slew rate does not limit the adc? performance. the input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by -3db. full-power bandwidth a large -0.5dbfs analog input signal is applied to an adc, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by -3db. this point is defined as full- power input bandwidth frequency. gain matching gain matching is a figure of merit that indicates how well the gain of all eight adc channels is matched to each other. for the max1436b, gain matching is mea- sured by applying the same 5.3mhz, -0.5dbfs analog signal to all analog input channels. these analog inputs are sampled at 40msps and the maximum deviation in amplitude is reported in db as gain matching in the electrical characteristics table. phase matching phase matching is a figure of merit that indicates how well the phases of all eight adc channels are matched to each other. for the max1436b, phase matching is measured by applying the same 5.3mhz, -0.5dbfs analog signal to all analog input channels. these ana- log inputs are sampled at 40msps and the maximum deviation in phase is reported in degrees as phase matching in the electrical characteristics table.
max1436b octal, 12-bit, 40msps, 1.8v adc with serial lvds outputs 22 ______________________________________________________________________________________ n.c. ovdd out1n ovdd out2n ovdd n.c. n.c. out2p out1p out3p ovdd ovdd ovdd framep clkoutp clkoutn out3n ovdd out4p out5p out5n out4n ovdd framen in1n gnd in2p gnd in3p in3n gnd in1p gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 gnd n.c. dt cvdd n.c. in7n in7p gnd gnd gnd in0n in0p gnd cmout refadj refio gnd refp refn gnd avdd avdd avdd pll1 pll2 pll3 stby lvdstest out0p out0n ovdd n.c. gnd max1436b top view in2n avdd avdd avdd avdd gnd in4p gnd n.c. in4n gnd in5p gnd in6p in6n in5n avdd avdd avdd avdd avdd gnd clk avdd out7p ovdd out6n 0vdd out7n ovdd out6p tqfp 14mm x 14mm x 1mm + slvs/lvds t/b *ep *connect ep to gnd pin configuration chip information process: bicmos
max1436b octal, 12-bit, 40msps, 1.8v adc with serial lvds outputs ______________________________________________________________________________________ 23 package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a "+", "#", or "-" in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing per - tains to the package regardless of rohs status. package type package code outline no. land pattern no. 100 tqfp-ep c100e+2 21-0116 90-0153
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 24 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. springer octal, 12-bit, 40msps, 1.8v adc with serial lvds outputs max1436b revision history revision number revision date description pages changed 0 3/06 initial release 1 2/11 updated ordering information , added new package thermal characteristics section, and fixed errors in electrical characteristics table 1?

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